While single-chip Bluetooth Low Energy (Bluetooth LE) Systems-on-Chip (SoCs) have been available since Nordic launched the nRF51 Series in 2012, until recently they lacked the computing power for the most complex wearable applications. This situation forced developers to increase solution complexity and extend design schedules by specifying a two-chip Bluetooth LE solution comprising a connectivity chip (essentially the radio) teamed with a supervisory microprocessor.
That changed with Nordic’s 2015 launch of the nRF52832 (and more recently the nRF52840) which combines a higher performance microprocessor with a higher sensitivity radio, and greater RAM and
Flash memory capacity to support more advanced RF software protocols (“stacks”) and sophisticated application code. These nRF52 Series SoCs free developers to design complex applications without having to resort
to two-chip designs.
Single-chip solutions bring other advantages, including: Less PCB area; lower bill-of- material (BOM); elimination of the power- and performance-sapping interface between separate connectivity chip and microprocessor; simplification of software architecture by elimination of code split between the two chips; simpler software development due to the requirement for a single toolchain, and debug of just one coding language.
Since its launch as a hallmark element of Bluetooth 4.0 back in 2010, Bluetooth LE applications have rapidly increased in complexity as the technology extends far beyond the original target sectors.
For example, a typical high-end wearable supports routine features such as activity monitoring, calorie consumption, sleep pattern monitoring, as well as more focused analytics such as heart rate variability (measurement of the time between heart beats), skin temperature, and muscle oxygen levels. Information comes from accelerometers, gyroscopes, and pulse oximeters every tens or hundreds of milliseconds.
Such sensors require the Bluetooth LE SoC’s processor to be capable of rapid Digital Signal Processing (DSP) and Floating-Point (FP) arithmetic to deal with this constant stream of data and transform it into accurate and precise activity, sleep, and heart rate data. DSP transforms the analog sensors’ signals into the digital domain while FP arithmetic uses a formulaic representation of real numbers to accommodate a much wider range of values. A number is typically represented by a fixed number of significant digits and scaled using an exponent in a fixed base. Such DSP and FP arithmetic are common challenges for developers of high-end wearables.
Nordic’s nRF52832 and nRF52840 SoCs’ ARM M4F microprocessors are perfectly adapted for DSP and FP arithmetic. For example, Figure 1 compares how much more rapidly the 64 MHz, 32-bit ARM M4F-powered nRF52832 SoC performs a software based floating-point operation (Fast Fourier Transform (FFT) q31) compared with a 16-MHz, 32-bit ARM M0-powered nRF51822. (FFT is a commonly employed algorithm used to convert a discrete time-domain signal into an equivalent frequency-domain signal. q31 is a common data format used for FFT calculations.)
It’s important to note that comparing an ARM M0 to an M4F microprocessor isn’t just about the clock speed, FP, and DSP capabilities. The structure of the microprocessors is different with the ARM M4F based on Harvard architecture contrasted with the M0’s Von Neumann; making
it impossible to make a direct comparison. For example, if the respective microprocessors are running filters and polynomial-based computations the M4F’s Harvard architecture is inherently faster no matter what the chip clock speed.
However, rapid processor clocking will maximize the performance of the ARM M4F microprocessor. In the nRF52832 SoC the device runs at 64 MHz (compared to the nRF51822 SoC’s 16 MHz clock speed). Code execution at this clock speed requires the resources of the nRF52832 SoC’s larger instruction cache to ensure the embedded Flash memory access doesn’t create a bottleneck.
In addition to an efficient microprocessor, a Bluetooth LE SoC for complex applications demands enough RAM and Flash memory to support an RF stack and application software, and, crucially, over-the-air device firmware updates (OTA-DFU). Previously, designers leaned towards a two-chip approach because it offered not only flexibility in the choice of microprocessor but also the memory configuration. Today, the nRF52 Series SoCs embed up to 1MB Flash and 256 kB RAM so separate memory chips are not required.
Read part 2 here