Master boot record
The main functionality of the MBR is to provide an interface to allow in-system updates of the application, the SoftDevice, and bootloader firmware.
The MBR module occupies a defined region in the System on Chip (SoC) program memory where the System Vector table resides.
All exceptions (reset, hard fault, interrupts, Supervisor Call (SVC)s) are first processed by the MBR and then forwarded to the appropriate handlers (for example the bootloader or the SoftDevice exception handlers). For more information on the interrupt forwarding scheme, see Interrupt model and processor availability.
During a firmware update process, the MBR is never erased. The MBR ensures that the bootloader can recover from any unexpected resets during an ongoing update process.
When issuing the SD_MBR_COMMAND_COPY_BL or SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET commands, the
MBR requires a page in the application flash region (see Memory isolation and runtime protection)
for storing the MBR parameters. The address of this flash page is referred to as MBRPARAMADDR
(see MBR, SoftDevice, and bootloader architecture). The MBRPARAMADDR address can
be provided either at the
MBR_PARAM_ADDR flash memory location, which is
defined in nrf_mbr.h, or in the UICR.NRFFW register. Using the flash
memory location is the safest because it can be read/write protected. This is also the location that will be checked
first by the MBR. UICR.NRFFW is checked only if
MBR_PARAM_ADDR has the
default value, which is 0xFFFFFFFF.
When an MBRPARAMADDR address is provided, the page it refers to must not be used by the application. The page will be cleared by the MBR and used to store parameters before chip reset.
The MBR commands that require flash access will return
the MBRPARAMADDR address is not provided. If the MBR commands that require flash access are
not used, the application does not need to reserve the flash page, and it can leave the
MBR_PARAM_ADDR flash memory location and the UICR.NRFFW register as
0xFFFFFFFF, which is the default value.