POWER — Power supply

The power supply consists of a number of LDO and DC/DC regulators that are utilized to maximize the system's power efficiency.

This device has the following power supply features:

  • On-chip LDO and DC/DC regulators
  • Global System ON/OFF modes
  • Individual RAM section power control for all system modes
  • Analog or digital pin wakeup from System OFF
  • Supervisor hardware to manage power-on reset, brownout, and power failure
  • Auto-controlled refresh modes for LDO and DC/DC regulators to maximize efficiency
  • External circuitry supply
  • Separate USB supply

Main supply

The main supply voltage is connected to the VDD/VDDH pins. The system will enter one of two supply voltage modes, normal or high voltage mode, depending on how the supply voltage is connected to these pins.

Normal voltage mode is entered when the supply voltage is connected to both the VDD and VDDH pins (pin VDD shorted to pin VDDH). For the supply voltage range to connect to both VDD and VDDH pins see parameter VDD.

High voltage mode is entered when the supply voltage is only connected to the VDDH pin and the VDD pin is not connected to any voltage supply. For the supply voltage range to connect to VDDH pin see parameter VDDH.

The register MAINREGSTATUS can be used for reading out the current supply voltage mode.

Main voltage regulators

The system contains two main supply regulator stages, REG0 and REG1.

Each regulator stage has the following regulator type options:

  • Low-dropout regulator (LDO)
  • Buck regulator (DC/DC)

In normal voltage mode, only the REG1 regulator stage is used and the REG0 stage is automatically disabled. In high voltage mode, both regulator stages (REG0 and REG1) are used. The output voltage of REG0 can be configured in register REGOUT0. This output voltage is connected to VDD and is the input voltage to REG1.

By default, the LDO regulators are enabled and the DC/DC regulators are disabled. Registers DCDCEN0 and DCDCEN are used to independently enable the DC/DC regulators for the two stages (REG0 and REG1 respectively).

When a DC/DC converter is enabled, the LDO for the corresponding regulator stage will be disabled. External LC filters must be connected for each of the DC/DC regulators being used. The advantage of using a DC/DC regulator is that the overall power consumption is normally reduced as the efficiency of such a regulator is higher than that of a LDO. The efficiency benefit of using a DC/DC regulator becomes particularly prominent when the regulator voltage drop (difference between input and output voltage) is high. The efficiency of internal regulators vary with the supply voltage and the current drawn from the regulators.

Note: Do not enable DC/DC regulator without an external LC filter being connected as this will inhibit device operation, including debug access, until an LC filter is connected.

GPIO levels

The GPIO high reference voltage always equals the level on the VDD pin.

In normal voltage mode, the GPIO high level equals the voltage supplied to the VDD pin. In High Voltage mode it equals the level specified in register REGOUT0.

External circuitry supply

In High Voltage mode, the output from REG0 can be used to supply external circuitry from the VDD pin.

The VDD output voltage is configured in the register REGOUT0.

The supported output voltage range depends on the supply voltage provided on the VDDH pin. Minimum difference between voltage supplied on the VDDH pin and the voltage output on the VDD pin is defined by the VREG0,DROP parameter in Regulator specifications, REG0 stage.

Supplying external circuitry is allowed in both System OFF and System ON mode.

Note: The maximum allowed current drawn by external circuitry is dependent on the total internal current draw. The maximum current that can be drawn externally from REG0 is defined in Regulator specifications, REG0 stage).

Regulator configuration examples

The voltage regulators can be configured in several ways, depending on the selected Supply Voltage mode (normal/high) and the regulator type option (LDO or DC/DC).

Four configuration examples are illustrated in images below.

Figure 1. Normal Voltage mode, LDO only

Normal Voltage mode, LDO only

Figure 2. Normal Voltage mode, DC/DC REG1 enabled

Normal Voltage mode, DC/DC REG1 enabled

Figure 3. High Voltage mode, LDO only

High Voltage mode, LDO only

Figure 4. High Voltage mode, DC/DC for REG0 and REG1 enabled

High Voltage mode, DC/DC for REG0 and REG1 enabled

Power supply supervisor

The power supply supervisor enables monitoring of the connected power supply.

The power supply supervisor provides:

  • Power-on reset, signalling to the circuit when a supply is connected.
  • An optional power-fail comparator (POF), to signal the application when the supply voltages drop below a configured threshold.
  • A fixed brownout reset detector, to hold the system in reset when the voltage is too low for safe operation.

The power supply supervisor is illustrated in Power supply supervisor.

Figure 5. Power supply supervisor

Power supply supervisor

Power-fail comparator

Using the power-fail comparator (POF) is optional. When enabled, it can provide the CPU an early warning of an impending power supply failure.

To enable and configure the power-fail comparator, see the register POFCON.

When the supply voltage falls below the defined threshold, the power-fail comparator will generate an event (POFWARN) which can be used by an application to prepare for power failure. This event will also be generated if the supply voltage is already below the threshold at the time the power-fail comparator is enabled, or if the threshold is re-configured to a level above the supply voltage.

If the power failure warning is enabled and the supply voltage is below the threshold, the power-fail comparator will prevent the NVMC from performing write operations to the flash.

The comparator features a hysteresis of VHYST, as illustrated in Power-fail comparator (BOR = brownout reset).

Figure 6. Power-fail comparator (BOR = brownout reset)

Power-fail comparator (BOR = brownout reset)

To save power, the power-fail comparator is not active in System OFF or in System ON when HFCLK is not running.

USB supply

When using the USB peripheral, a 5 V USB supply needs to be provided on the VBUS pin.

The USB peripheral has a dedicated internal voltage regulator for converting the VBUS supply to 3.3 V used by the USB signalling interface (D+ and D- lines, and pull-up on D+). The rest of the USB peripheral (USBD) is supplied through the main supply like any other on-chip feature. As a consequence, both VBUS and either VDDH or VDD supplies are required for USB peripheral operation.

When VBUS rises into its valid range, the software is notified through a USBDETECTED event. A USBREMOVED event is sent when VBUS goes below its valid range. Use these events to implement the USBD start-up sequence described in the USBD chapter.

When VBUS rises into its valid range while the device is in System OFF, the device resets and transitions to System ON mode. The RESETREAS register will have the VBUS bit set to indicate the source of the wake-up.

See VBUS detection specifications for the levels at which the events are sent (VBUS,DETECT and VBUS,REMOVE) or at which the system is woken up from System OFF (VBUS,DETECT).

When the USBD peripheral is enabled through the ENABLE register, and VBUS is detected, the regulator is turned on. A USBPWRRDY event is sent when the regulator's worst case settling time has elapsed, indicating to the software that it can enable the USB pull-up to signal a USB connection to the host.

The software can read the state of the VBUS detection and regulator output readiness at any time through the USBREGSTATUS register.

Figure 7. USB voltage regulator

USB voltage regulator

To ensure stability, the input and output of the USB regulator need to be decoupled with a suitable decoupling capacitor. See Reference circuitry for the recommended values.

System OFF mode

System OFF is the deepest power saving mode the system can enter. In this mode, the system’s core functionality is powered down and all ongoing tasks are terminated.

The device can be put into System OFF mode using the register SYSTEMOFF. When in System OFF mode, the device can be woken up through one of the following signals:

  1. The DETECT signal, optionally generated by the GPIO peripheral.
  2. The ANADETECT signal, optionally generated by the LPCOMP module.
  3. The SENSE signal, optionally generated by the NFC module to wake-on-field.
  4. Detecting a valid USB voltage on the VBUS pin (VBUS,DETECT).
  5. A reset.

The system is reset when it wakes up from the System OFF mode.

One or more RAM sections can be retained in System OFF mode, depending on the settings in the RAM[n].POWER registers. RAM[n].POWER are retained registers. Note that these registers are usually overwritten by the start-up code provided with the nRF application examples.

Before entering the System OFF mode, the user must make sure that all on-going EasyDMA transactions have been completed. See peripheral specific chapters for more information about how to acquire the status of EasyDMA transactions.

Emulated System OFF mode

If the device is in Debug Interface mode, System OFF will be emulated to secure that all required resources needed for debugging are available during System OFF.

See Debug and trace for more information. Required resources needed for debugging include the following key components: Debug and trace, CLOCK — Clock control, POWER — Power supply, NVMC — Non-volatile memory controller, CPU, flash, and RAM. Since the CPU is kept on in an emulated System OFF mode, it is recommended to add an infinite loop directly after entering System OFF, to prevent the CPU from executing code that normally should not be executed.

System ON mode

System ON is the default state after power-on reset. In System ON, all functional blocks such as the CPU or peripherals can be in IDLE or RUN mode, depending on the configuration set by the software and the state of the application executing.

Register RESETREAS provides information about the source causing the wakeup or reset.

The system can switch the appropriate internal power sources on and off, depending on how much power is needed at any given time. The power requirement of a peripheral is directly related to its activity level, and the activity level of a peripheral is usually raised and lowered when specific tasks are triggered or events are generated.

Sub power modes

In System ON mode, when both the CPU and all the peripherals are in IDLE mode, the system can reside in one of the two sub power modes.

The sub power modes are:

  • Constant Latency
  • Low-power

In Constant Latency mode, the CPU wakeup latency and the PPI task response are constant and kept at a minimum. This is secured by forcing a set of basic resources to be turned on while in sleep. Having a constant and predictable latency is at the cost of having increased power consumption. The Constant Latency mode is selected by triggering the CONSTLAT task.

In Low-power mode, the automatic power management system described in System ON mode ensures that the most efficient supply option is chosen to save most power. Having the lowest power possible is at the cost of having a varying CPU wakeup latency and PPI task response. The Low-power mode is selected by triggering the LOWPWR task.

When the system enters System ON mode, it is by default in Low-power sub power mode.

RAM power control

The RAM power control registers are used for configuring the following:

  • The RAM sections to be retained during System OFF
  • The RAM sections to be retained and accessible during System ON

In System OFF, retention of a RAM section is configured in the RETENTION field of the corresponding register RAM[n].POWER (n=0..8).

In System ON, retention and accessibility for a RAM section is configured in the RETENTION and POWER fields of the corresponding register RAM[n].POWER (n=0..8).

The following table summarizes the behavior of these registers.

Table 1. RAM section configuration. x = don't care.
Configuration RAM section status
System on/off RAM[n].POWER.POWER RAM[n].POWER.RETENTION Accessible Retained
Off x Off No No
Off x On No Yes
On Off Off No No
On Off1 On No Yes
On On x Yes Yes

The advantage of not retaining RAM contents is that the overall current consumption is reduced.

See chapter Memory for more information on RAM sections.

Reset

Several sources may trigger a reset.

After a reset has occurred, register RESETREAS can be read to determine which source has triggered the reset.

Power-on reset

The power-on reset generator initializes the system at power-on.

The system is held in reset state until the supply has reached the minimum operating voltage and the internal voltage regulators have started.

Pin reset

A pin reset is generated when the physical reset pin on the device is asserted.

Pin reset is configured via the PSELRESET[0] and PSELRESET[1] registers.

Wakeup from System OFF mode reset

The device is reset when it wakes up from System OFF mode.

The debug access port (DAP) is not reset following a wake up from System OFF mode if the device is in Debug Interface mode. See chapter Debug and trace for more information.

Soft reset

A soft reset is generated when the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR) in the ARM® core is set.

See ARM documentation for more details.

A soft reset can also be generated via the register RESET in the CTRL-AP.

Watchdog reset

A Watchdog reset is generated when the watchdog times out.

See chapter WDT — Watchdog timer for more information.

Brownout reset

The brownout reset generator puts the system in reset state if VDD drops below the brownout reset (BOR) threshold.

See section Power fail comparator for more information.

Retained registers

A retained register is a register that will retain its value in System OFF mode and through a reset, depending on reset source. See the individual peripheral chapters for information on which of their registers are retained.

Reset behavior

The various reset sources and their targets are summarized in the table below.

Reset source Reset target
CPU Peripherals GPIO Debuga SWJ-DP RAM WDT Retained registers RESETREAS
CPU lockup 3 x x x
Soft reset x x x
Wakeup from System OFF mode reset x x x 4 x 5
Watchdog reset 6 x x x x x x x
Pin reset x x x x x x x
Brownout reset x x x x x x x x x
Power-on reset x x x x x x x x x
Note: The RAM is never reset, but depending on a reset source the content of RAM may be corrupted.

Registers

Table 2. Instances
Base address Peripheral Instance Description Configuration
0x40000000 POWER POWER

Power control

Table 3. Register overview
Register Offset Description
TASKS_CONSTLAT 0x78

Enable Constant Latency mode

TASKS_LOWPWR 0x7C

Enable Low-power mode (variable latency)

EVENTS_POFWARN 0x108

Power failure warning

EVENTS_SLEEPENTER 0x114

CPU entered WFI/WFE sleep

EVENTS_SLEEPEXIT 0x118

CPU exited WFI/WFE sleep

EVENTS_USBDETECTED 0x11C

Voltage supply detected on VBUS

EVENTS_USBREMOVED 0x120

Voltage supply removed from VBUS

EVENTS_USBPWRRDY 0x124

USB 3.3 V supply ready

INTENSET 0x304

Enable interrupt

INTENCLR 0x308

Disable interrupt

RESETREAS 0x400

Reset reason

RAMSTATUS 0x428

RAM status register

Deprecated

USBREGSTATUS 0x438

USB supply status

SYSTEMOFF 0x500

System OFF register

POFCON 0x510

Power-fail comparator configuration

GPREGRET 0x51C

General purpose retention register

GPREGRET2 0x520

General purpose retention register

DCDCEN 0x578

Enable DC/DC converter for REG1 stage

DCDCEN0 0x580

Enable DC/DC converter for REG0 stage

MAINREGSTATUS 0x640

Main supply status

RAM[0].POWER 0x900

RAM0 power control register

RAM[0].POWERSET 0x904

RAM0 power control set register

RAM[0].POWERCLR 0x908

RAM0 power control clear register

RAM[1].POWER 0x910

RAM1 power control register

RAM[1].POWERSET 0x914

RAM1 power control set register

RAM[1].POWERCLR 0x918

RAM1 power control clear register

RAM[2].POWER 0x920

RAM2 power control register

RAM[2].POWERSET 0x924

RAM2 power control set register

RAM[2].POWERCLR 0x928

RAM2 power control clear register

RAM[3].POWER 0x930

RAM3 power control register

RAM[3].POWERSET 0x934

RAM3 power control set register

RAM[3].POWERCLR 0x938

RAM3 power control clear register

RAM[4].POWER 0x940

RAM4 power control register

RAM[4].POWERSET 0x944

RAM4 power control set register

RAM[4].POWERCLR 0x948

RAM4 power control clear register

RAM[5].POWER 0x950

RAM5 power control register

RAM[5].POWERSET 0x954

RAM5 power control set register

RAM[5].POWERCLR 0x958

RAM5 power control clear register

RAM[6].POWER 0x960

RAM6 power control register

RAM[6].POWERSET 0x964

RAM6 power control set register

RAM[6].POWERCLR 0x968

RAM6 power control clear register

RAM[7].POWER 0x970

RAM7 power control register

RAM[7].POWERSET 0x974

RAM7 power control set register

RAM[7].POWERCLR 0x978

RAM7 power control clear register

RAM[8].POWER 0x980

RAM8 power control register

RAM[8].POWERSET 0x984

RAM8 power control set register

RAM[8].POWERCLR 0x988

RAM8 power control clear register

TASKS_CONSTLAT

Address offset: 0x78

Enable Constant Latency mode

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_CONSTLAT

Enable Constant Latency mode

Trigger

1

Trigger task

TASKS_LOWPWR

Address offset: 0x7C

Enable Low-power mode (variable latency)

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

TASKS_LOWPWR

Enable Low-power mode (variable latency)

Trigger

1

Trigger task

EVENTS_POFWARN

Address offset: 0x108

Power failure warning

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_POFWARN

Power failure warning

NotGenerated

0

Event not generated

Generated

1

Event generated

EVENTS_SLEEPENTER

Address offset: 0x114

CPU entered WFI/WFE sleep

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_SLEEPENTER

CPU entered WFI/WFE sleep

NotGenerated

0

Event not generated

Generated

1

Event generated

EVENTS_SLEEPEXIT

Address offset: 0x118

CPU exited WFI/WFE sleep

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_SLEEPEXIT

CPU exited WFI/WFE sleep

NotGenerated

0

Event not generated

Generated

1

Event generated

EVENTS_USBDETECTED

Address offset: 0x11C

Voltage supply detected on VBUS

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_USBDETECTED

Voltage supply detected on VBUS

NotGenerated

0

Event not generated

Generated

1

Event generated

EVENTS_USBREMOVED

Address offset: 0x120

Voltage supply removed from VBUS

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_USBREMOVED

Voltage supply removed from VBUS

NotGenerated

0

Event not generated

Generated

1

Event generated

EVENTS_USBPWRRDY

Address offset: 0x124

USB 3.3 V supply ready

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

EVENTS_USBPWRRDY

USB 3.3 V supply ready

NotGenerated

0

Event not generated

Generated

1

Event generated

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

F

E

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

POFWARN

Write '1' to enable interrupt for event POFWARN

Set

1

Enable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

B RW

SLEEPENTER

Write '1' to enable interrupt for event SLEEPENTER

Set

1

Enable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

C RW

SLEEPEXIT

Write '1' to enable interrupt for event SLEEPEXIT

Set

1

Enable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

D RW

USBDETECTED

Write '1' to enable interrupt for event USBDETECTED

Set

1

Enable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

E RW

USBREMOVED

Write '1' to enable interrupt for event USBREMOVED

Set

1

Enable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

F RW

USBPWRRDY

Write '1' to enable interrupt for event USBPWRRDY

Set

1

Enable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

F

E

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

POFWARN

Write '1' to disable interrupt for event POFWARN

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

B RW

SLEEPENTER

Write '1' to disable interrupt for event SLEEPENTER

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

C RW

SLEEPEXIT

Write '1' to disable interrupt for event SLEEPEXIT

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

D RW

USBDETECTED

Write '1' to disable interrupt for event USBDETECTED

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

E RW

USBREMOVED

Write '1' to disable interrupt for event USBREMOVED

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

F RW

USBPWRRDY

Write '1' to disable interrupt for event USBPWRRDY

Clear

1

Disable

Disabled

0

Read: Disabled

Enabled

1

Read: Enabled

RESETREAS

Address offset: 0x400

Reset reason

Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing '1' to it. If none of the reset sources are flagged, this indicates that the chip was reset from the on-chip reset generator, which will indicate a power-on-reset or a brownout reset.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

I

H

G

F

E

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

RESETPIN

Reset from pin-reset detected

NotDetected

0

Not detected

Detected

1

Detected

B RW

DOG

Reset from watchdog detected

NotDetected

0

Not detected

Detected

1

Detected

C RW

SREQ

Reset from soft reset detected

NotDetected

0

Not detected

Detected

1

Detected

D RW

LOCKUP

Reset from CPU lock-up detected

NotDetected

0

Not detected

Detected

1

Detected

E RW

OFF

Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO

NotDetected

0

Not detected

Detected

1

Detected

F RW

LPCOMP

Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP

NotDetected

0

Not detected

Detected

1

Detected

G RW

DIF

Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode

NotDetected

0

Not detected

Detected

1

Detected

H RW

NFC

Reset due to wake up from System OFF mode by NFC field detect

NotDetected

0

Not detected

Detected

1

Detected

I RW

VBUS

Reset due to wake up from System OFF mode by VBUS rising into valid range

NotDetected

0

Not detected

Detected

1

Detected

RAMSTATUS ( Deprecated )

Address offset: 0x428

RAM status register

Since this register is deprecated the following substitutions have been made: RAM block 0 is equivalent to a block comprising RAM0.S0 and RAM1.S0, RAM block 1 is equivalent to a block comprising RAM2.S0 and RAM3.S0, RAM block 2 is equivalent to a block comprising RAM4.S0 and RAM5.S0 and RAM block 3 is equivalent to a block comprising RAM6.S0 and RAM7.S0. A RAM block field will indicate ON as long as any of the RAM sections associated with a block are on.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A-D R

RAMBLOCK[i] (i=0..3)

RAM block i is on or off/powering up

Off

0

Off

On

1

On

USBREGSTATUS

Address offset: 0x438

USB supply status

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A R

VBUSDETECT

VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information)

NoVbus

0

VBUS voltage below valid threshold

VbusPresent

1

VBUS voltage above valid threshold

B R

OUTPUTRDY

USB supply output settling time elapsed

NotReady

0

USBREG output settling time not elapsed

Ready

1

USBREG output settling time elapsed (same information as USBPWRRDY event)

SYSTEMOFF

Address offset: 0x500

System OFF register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

SYSTEMOFF

Enable System OFF mode

Enter

1

Enable System OFF mode

POFCON

Address offset: 0x510

Power-fail comparator configuration

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

D

D

D

D

B

B

B

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

POF

Enable or disable power failure warning

Disabled

0

Disable

Enabled

1

Enable

B RW

THRESHOLD

Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages.

V17

4

Set threshold to 1.7 V

V18

5

Set threshold to 1.8 V

V19

6

Set threshold to 1.9 V

V20

7

Set threshold to 2.0 V

V21

8

Set threshold to 2.1 V

V22

9

Set threshold to 2.2 V

V23

10

Set threshold to 2.3 V