Nordic Semiconductor nRF5 AirFuel SDK  version 2.2.0
nrf_drv_config.h
1 /* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
2  *
3  * The information contained herein is property of Nordic Semiconductor ASA.
4  * Terms and conditions of usage are described in detail in NORDIC
5  * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
6  *
7  * Licensees are granted free, non-transferable use of the information. NO
8  * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
9  * the file.
10  *
11  */
12 
20 #ifndef NRF_DRV_CONFIG_H
21 #define NRF_DRV_CONFIG_H
22 
34 #define PERIPHERAL_RESOURCE_SHARING_ENABLED 0
35 
36 /* CLOCK */
37 #define CLOCK_ENABLED 0
38 
39 #if (CLOCK_ENABLED == 1)
40 #define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
41 #define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LF_SRC_Xtal
42 #define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
43 #endif
44 
45 /* GPIOTE */
46 #define GPIOTE_ENABLED 0
47 
48 #if (GPIOTE_ENABLED == 1)
49 #define GPIOTE_CONFIG_USE_SWI_EGU false
50 #define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
51 #define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
52 #endif
53 
54 /* TIMER */
55 #define TIMER0_ENABLED 0
56 
57 #if (TIMER0_ENABLED == 1)
58 #define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
59 #define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
60 #define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
61 #define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
62 
63 #define TIMER0_INSTANCE_INDEX 0
64 #endif
65 
66 #define TIMER1_ENABLED 0
67 
68 #if (TIMER1_ENABLED == 1)
69 #define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
70 #define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
71 #define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
72 #define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
73 
74 #define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
75 #endif
76 
77 #define TIMER2_ENABLED 0
78 
79 #if (TIMER2_ENABLED == 1)
80 #define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
81 #define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
82 #define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
83 #define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
84 
85 #define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
86 #endif
87 
88 #define TIMER3_ENABLED 0
89 
90 #if (TIMER3_ENABLED == 1)
91 #define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
92 #define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
93 #define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
94 #define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
95 
96 #define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
97 #endif
98 
99 #define TIMER4_ENABLED 0
100 
101 #if (TIMER4_ENABLED == 1)
102 #define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
103 #define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
104 #define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
105 #define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
106 
107 #define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
108 #endif
109 
110 
111 #define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
112 
113 /* RTC */
114 #define RTC0_ENABLED 0
115 
116 #if (RTC0_ENABLED == 1)
117 #define RTC0_CONFIG_FREQUENCY 32678
118 #define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
119 #define RTC0_CONFIG_RELIABLE false
120 
121 #define RTC0_INSTANCE_INDEX 0
122 #endif
123 
124 #define RTC1_ENABLED 0
125 
126 #if (RTC1_ENABLED == 1)
127 #define RTC1_CONFIG_FREQUENCY 32768
128 #define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
129 #define RTC1_CONFIG_RELIABLE false
130 
131 #define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
132 #endif
133 
134 #define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED)
135 
136 #define NRF_MAXIMUM_LATENCY_US 2000
137 
138 /* RNG */
139 #define RNG_ENABLED 0
140 
141 #if (RNG_ENABLED == 1)
142 #define RNG_CONFIG_ERROR_CORRECTION true
143 #define RNG_CONFIG_POOL_SIZE 8
144 #define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
145 #endif
146 
147 /* PWM */
148 
149 #define PWM0_ENABLED 0
150 
151 #if (PWM0_ENABLED == 1)
152 #define PWM0_CONFIG_OUT0_PIN 2
153 #define PWM0_CONFIG_OUT1_PIN 3
154 #define PWM0_CONFIG_OUT2_PIN 4
155 #define PWM0_CONFIG_OUT3_PIN 5
156 #define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
157 #define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
158 #define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
159 #define PWM0_CONFIG_TOP_VALUE 1000
160 #define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
161 #define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
162 
163 #define PWM0_INSTANCE_INDEX 0
164 #endif
165 
166 #define PWM1_ENABLED 0
167 
168 #if (PWM1_ENABLED == 1)
169 #define PWM1_CONFIG_OUT0_PIN 2
170 #define PWM1_CONFIG_OUT1_PIN 3
171 #define PWM1_CONFIG_OUT2_PIN 4
172 #define PWM1_CONFIG_OUT3_PIN 5
173 #define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
174 #define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
175 #define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
176 #define PWM1_CONFIG_TOP_VALUE 1000
177 #define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
178 #define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
179 
180 #define PWM1_INSTANCE_INDEX (PWM0_ENABLED)
181 #endif
182 
183 #define PWM2_ENABLED 0
184 
185 #if (PWM2_ENABLED == 1)
186 #define PWM2_CONFIG_OUT0_PIN 2
187 #define PWM2_CONFIG_OUT1_PIN 3
188 #define PWM2_CONFIG_OUT2_PIN 4
189 #define PWM2_CONFIG_OUT3_PIN 5
190 #define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
191 #define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
192 #define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
193 #define PWM2_CONFIG_TOP_VALUE 1000
194 #define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
195 #define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
196 
197 #define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED)
198 #endif
199 
200 #define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED)
201 
202 /* SPI */
203 #define SPI0_ENABLED 0
204 
205 #if (SPI0_ENABLED == 1)
206 #define SPI0_USE_EASY_DMA 0
207 
208 #define SPI0_CONFIG_SCK_PIN 2
209 #define SPI0_CONFIG_MOSI_PIN 3
210 #define SPI0_CONFIG_MISO_PIN 4
211 #define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
212 
213 #define SPI0_INSTANCE_INDEX 0
214 #endif
215 
216 #define SPI1_ENABLED 0
217 
218 #if (SPI1_ENABLED == 1)
219 #define SPI1_USE_EASY_DMA 0
220 
221 #define SPI1_CONFIG_SCK_PIN 2
222 #define SPI1_CONFIG_MOSI_PIN 3
223 #define SPI1_CONFIG_MISO_PIN 4
224 #define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
225 
226 #define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
227 #endif
228 
229 #define SPI2_ENABLED 0
230 
231 #if (SPI2_ENABLED == 1)
232 #define SPI2_USE_EASY_DMA 0
233 
234 #define SPI2_CONFIG_SCK_PIN 2
235 #define SPI2_CONFIG_MOSI_PIN 3
236 #define SPI2_CONFIG_MISO_PIN 4
237 #define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
238 
239 #define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
240 #endif
241 
242 #define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
243 
244 /* SPIS */
245 #define SPIS0_ENABLED 0
246 
247 #if (SPIS0_ENABLED == 1)
248 #define SPIS0_CONFIG_SCK_PIN 2
249 #define SPIS0_CONFIG_MOSI_PIN 3
250 #define SPIS0_CONFIG_MISO_PIN 4
251 #define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
252 
253 #define SPIS0_INSTANCE_INDEX 0
254 #endif
255 
256 #define SPIS1_ENABLED 0
257 
258 #if (SPIS1_ENABLED == 1)
259 #define SPIS1_CONFIG_SCK_PIN 2
260 #define SPIS1_CONFIG_MOSI_PIN 3
261 #define SPIS1_CONFIG_MISO_PIN 4
262 #define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
263 
264 #define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
265 #endif
266 
267 #define SPIS2_ENABLED 0
268 
269 #if (SPIS2_ENABLED == 1)
270 #define SPIS2_CONFIG_SCK_PIN 2
271 #define SPIS2_CONFIG_MOSI_PIN 3
272 #define SPIS2_CONFIG_MISO_PIN 4
273 #define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
274 
275 #define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
276 #endif
277 
278 #define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
279 
280 /* UART */
281 #define UART0_ENABLED 0
282 
283 #if (UART0_ENABLED == 1)
284 #define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED
285 #define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
286 #define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_38400
287 #define UART0_CONFIG_PSEL_TXD 0
288 #define UART0_CONFIG_PSEL_RXD 0
289 #define UART0_CONFIG_PSEL_CTS 0
290 #define UART0_CONFIG_PSEL_RTS 0
291 #define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
292 #ifdef NRF52
293 #define UART0_CONFIG_USE_EASY_DMA false
294 //Compile time flag
295 #define UART_EASY_DMA_SUPPORT 1
296 #define UART_LEGACY_SUPPORT 1
297 #endif //NRF52
298 #endif
299 
300 #define TWI0_ENABLED 0
301 
302 #if (TWI0_ENABLED == 1)
303 #define TWI0_USE_EASY_DMA 0
304 
305 #define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
306 #define TWI0_CONFIG_SCL 0
307 #define TWI0_CONFIG_SDA 1
308 #define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
309 
310 #define TWI0_INSTANCE_INDEX 0
311 #endif
312 
313 #define TWI1_ENABLED 0
314 
315 #if (TWI1_ENABLED == 1)
316 #define TWI1_USE_EASY_DMA 0
317 
318 #define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
319 #define TWI1_CONFIG_SCL 0
320 #define TWI1_CONFIG_SDA 1
321 #define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
322 
323 #define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
324 #endif
325 
326 #define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED)
327 
328 /* TWIS */
329 #define TWIS0_ENABLED 0
330 
331 #if (TWIS0_ENABLED == 1)
332  #define TWIS0_CONFIG_ADDR0 0
333  #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
334  #define TWIS0_CONFIG_SCL 0
335  #define TWIS0_CONFIG_SDA 1
336  #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
337 
338  #define TWIS0_INSTANCE_INDEX 0
339 #endif
340 
341 #define TWIS1_ENABLED 0
342 
343 #if (TWIS1_ENABLED == 1)
344  #define TWIS1_CONFIG_ADDR0 0
345  #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
346  #define TWIS1_CONFIG_SCL 0
347  #define TWIS1_CONFIG_SDA 1
348  #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
349 
350  #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
351 #endif
352 
353 #define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
354 /* For more documentation see nrf_drv_twis.h file */
355 #define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
356 /* For more documentation see nrf_drv_twis.h file */
357 #define TWIS_NO_SYNC_MODE 0
358 
359 /* QDEC */
360 #define QDEC_ENABLED 0
361 
362 #if (QDEC_ENABLED == 1)
363 #define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
364 #define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
365 #define QDEC_CONFIG_PIO_A 1
366 #define QDEC_CONFIG_PIO_B 2
367 #define QDEC_CONFIG_PIO_LED 3
368 #define QDEC_CONFIG_LEDPRE 511
369 #define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
370 #define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
371 #define QDEC_CONFIG_DBFEN false
372 #define QDEC_CONFIG_SAMPLE_INTEN false
373 #endif
374 
375 /* SAADC */
376 #define SAADC_ENABLED 0
377 
378 #if (SAADC_ENABLED == 1)
379 #define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
380 #define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
381 #define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
382 #endif
383 
384 /* PDM */
385 #define PDM_ENABLED 0
386 
387 #if (PDM_ENABLED == 1)
388 #define PDM_CONFIG_MODE NRF_PDM_MODE_MONO
389 #define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING
390 #define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K
391 #define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
392 #endif
393 
394 /* LPCOMP */
395 #define LPCOMP_ENABLED 0
396 
397 #if (LPCOMP_ENABLED == 1)
398 #define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
399 #define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
400 #define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
401 #define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
402 #endif
403 
404 /* WDT */
405 #define WDT_ENABLED 0
406 
407 #if (WDT_ENABLED == 1)
408 #define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
409 #define WDT_CONFIG_RELOAD_VALUE 2000
410 #define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
411 #endif
412 
413 /* SWI EGU */
414 #ifdef NRF52
415  #define EGU_ENABLED 0
416 #endif
417 
418 /* I2S */
419 #define I2S_ENABLED 0
420 
421 #if (I2S_ENABLED == 1)
422 #define I2S_CONFIG_SCK_PIN 22
423 #define I2S_CONFIG_LRCK_PIN 23
424 #define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED
425 #define I2S_CONFIG_SDOUT_PIN 24
426 #define I2S_CONFIG_SDIN_PIN 25
427 #define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
428 #define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER
429 #define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S
430 #define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT
431 #define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT
432 #define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO
433 #define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8
434 #define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X
435 #endif
436 
437 #include "nrf_drv_config_validation.h"
438 
439 #endif // NRF_DRV_CONFIG_H
440