The nAD12xx-25b is a monolithic, high-speed, low power, analog-to-digital converter silicon IP with MiM capacitor option. It uses fully differential multistage pipeline architecture with digital error correction to provide 12-bit accuracy from 10 to 60 MSPS conversion speed. The core includes a sample-and-hold and an internal voltage reference that provides a nominal full-scale range of 2.0 V peak-to-peak. The IP is designed for high dynamic performance at input frequencies up to Nyquist and beyond.  It thus represents an ideal solution for demanding applications like broadband communication, imaging and multimedia.

The ADC consumes only 150 mW at 60 MSPS operation. Dynamic power scaling means that the power consumption scales linearly with approximately ~2.5 mW per MSPS Combined with power saving idle modes the ADC is suitable for battery powered devices. Output data is available in a binary offset coded format. Three out-of-range indicator bits are also available for determining if the input signal is over-range, under-range or out-of-range.

This family of converters is available in 0.25µm processes at TSMC.

(xxx=sampling speed in MSPS)